We are searching for our client, an IT company, a Digital Design Engineer to join their business in Romania..

Position Title:

Digital Design Engineer

Position Type

Contract (Full time)

Start Date:

ASAP

Location:

Romania

Contact:

Iulia Balan | +49(0)8923889862

Overview

• We are looking for a Digital Design Engineer to join our client’s hardware development teams working on complex ASIC and FPGA-based systems.
• The role targets mid to senior engineers with strong fundamentals in RTL design, SoC integration, and verification, capable of contributing across various application domains such as semiconductor, automotive, networking, security, and industrial systems.
• You will take part in the full development lifecycle, from architecture and RTL implementation to verification, integration, and silicon readiness.

Responsibilities

• Design, implement, and maintain RTL blocks using SystemVerilog and/or VHDL
• Contribute to SoC or subsystem architecture and top-level integration
• Integrate internal and third-party IPs, including interconnects and peripherals
• Handle Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) challenges
• Run and analyze lint, CDC, and design quality checks
• Support functional verification and debug simulation issues.
• Participate in design reviews and methodology improvements
• Support silicon bring-up or FPGA prototyping when required
• Produce clear technical documentation for designed blocks

Requirements

Core Digital Design

• Strong experience in RTL design (SystemVerilog and/or VHDL)
• Solid understanding of digital design fundamentals (timing, FSMs, datapaths)
• Experience with multi-clock and multi-reset designs
• Familiarity with ASIC and/or FPGA design flows

SoC & System Integration

• Experience integrating blocks within SoC or complex subsystems
• Knowledge of standard on-chip buses: AXI, AHB, APB
• Ability to interpret architectural and interface specifications

Verification & Quality

• Experience working with lint and CDC tools
• Ability to debug RTL and simulation failures
• Exposure to SystemVerilog assertions or UVM is a plus

Nice to Have

• Experience with high-speed or complex interfaces such as:

• LPDDR / LPDDR4 / LPDDR5
• PCI Express (any generation)
• Ethernet (1G to 100G, MAC/PCS)

• Low-power design concepts (UPF, power domains)
• Formal verification exposure
• FPGA prototyping and board bring-up
• Experience in automotive, networking, telecom, security, or aerospace projects
• Scripting skills (Python, TCL, Perl)
• Experience mentoring junior engineers

Seniority Guidance

• Mid-level: 5–8 years experience, strong hands-on RTL design, module ownership
• Senior-level: 8+ years experience, capable of owning architecture and integration

What We Offer

• Involvement in complex, real silicon projects
• Exposure to a wide range of technologies and domains
• Flexible work setup and competitive compensation
• Collaborative environment with strong technical expertise

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