THE ROLE:
This role will focus on planning, micro architect, documenting, code and debug the RTL for new and existing features for AMD’s Infinity Data Fabric with focus on complexity, timing, area and power consumption efficiency.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites and time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
•Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be designed
•Micro architect the feature, document it, estimate the effort and review the implementation with RTL lead and verification team
•Execute the RTL code of the new feature at best quality and within the estimated duration
•Debug and fix the RTL bugs, fix timing, area and power consumption issues
•Debug support for SOC simulation, emulation and actual silicon bring-up in lab
•Analyze code coverage and detect holes in the verification environment
null